1. Field of the Invention
This invention relates to semiconductor devices and more particularly to thin film transistors.
2. Description of the Prior Art
FIG. 5 shows a cross section of an example of a conventional amorphous silicon thin film transistor. A transparent insulating substrate 21 is provided thereon with a gate electrode 22 using chrome (Cr), and a gate insulating layer 23 that consists of silicon nitride formed by a plasma CVD process. A semiconductor layer 24 using amorphous silicon is formed on the gate insulating layer 23, and a source electrode 25 and a drain electrode 26 are formed by depositing and etching aluminum (Al).
FIG. 6 shows the electrical characteristics of the conventional amorphous silicon thin film transistor shown in FIG. 5. The curve (1) of FIG. 6 shows the drain current-gate voltage (I.sub.d -V.sub.g) characteristics at an initial state where the voltage between the source and the drain (V.sub.sd) was set for 10 volts. The threshold voltage (V.sub.th) at the moment was 1.2 volts. The curve (2) of FIG. 6 shows the I.sub.d -V.sub.g characteristics after applying +25 volts to the gate voltage of this amorphous silicon thin film transistor with constant source-drain voltage (V.sub.sd)=10 volts, leaving it for 96 hours. The curve (3) of FIG. 6 similarly shows the I.sub.d -V.sub.g characteristics after applying -10 volts to the gate voltage and leaving for 96 hours. The threshold voltage of the curves (2) and (3) of FIG. 6 is 2.1 and -0.3 volts, respectively.
As seen from FIG. 6, in the conventional amorphous silicon thin film transistor with the structure of FIG. 5, the threshold voltage (V.sub.th) shifts in the positive direction when a positive potential is applied to the gate voltage and left, and in the negative direction when a negative potential is applied and left. The amount of the shift is particularly significant in the positive direction. The variation of the threshold voltage (V.sub.th) appears to be caused by the fact that electric charges are implanted in the gate insulating layer 23.
Also, a similar variation of the threshold voltage (V.sub.th) is observed on the conventional amorphous silicon thin film transistor for temperature change. The charge implanted into the gate insulating layer 23, which appears to be the cause of those variations of the threshold voltage (V.sub.th), is caused by the gate voltage and the source voltage/current, but mainly by the gate voltage.
As described, the variation of the threshold voltage (V.sub.th) of the conventional amorphous silicon thin film transistor is very sensitive to external stress such as the gate voltage and temperature, which causes a very significant problem in stable operation and reliability.